Xilinx is looking for a highly qualified IC design engineer to join the clocking hardware design team. This individual will work on digital design of clock management blocks (eg, PLL, DLL) and clock distribution for next generation FPGAs. The engineer will be involved in the entire design process including RTL design and functional verification, schematic generation and/or synthesis, place and route, timing and electrical verification, and working with test engineers on silicon verification and characterization.


Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

Aerospace/Defense
Automotive
Broadcast
Consumer
High Performance Computing
Industrial / Scientific / Medical (ISM)
Wired
Wireless

Compliant Design Implementation
Exercises solid analytical problem solving in troubleshooting component designs (e.g., timing analysis, constraint setting)
Can run and implement designs (e.g., debugging, digital and analog design, circuit design, RTL signal flow, basic TCL coding, and timing tool basics)
Accurately documents and effectively communicates the rational for a design to design implementation stakeholders (e.g., peer reviews, Technical Solution Groups, management)
Coordinates with and manages external vendor deliverables
Mentors less experienced design engineers in implementation tasks to ensure compliance to specification, quality standards, and milestones

Design Implementation
Runs design models through EDA tools to anticipate and address implementation challenges prior to fabrication (i.e., 'pipe clean' tools)
Demonstrates a broad understanding of process technology and circuit capability in implementing component design
Exercises solid analytical problem solving in troubleshooting component designs (e.g., timing analysis, constraint setting)
Works efficiently and with agility to implement designs (e.g., transistor design, RTL coding, synthesis, conversion, linear dimension work, integration, verification)
Writes elegant, efficient code for devices or tools that avoid costly, overly complex solutions
Holds peer reviews of designs or methodologies to accommodate corrections, changing requirements, or new features
Accurately documents and effectively communicates the rational for a design to design implementation stakeholders (e.g., peers, Technical Solution Groups, management)
Applies systematic version control and tracking procedures to maintain quality source code
Coordinates with and manages external vendor deliverables

Design Process and Methodology
Demonstrates flexible adaptability in working with still maturing, generation-dependent design and testing methods
Provides design management (e.g., CAD department) with feedback on the efficiency of proposed methods and associated challenges, based on applied experience
Actively monitors Xilinx and industry communications for evolving design methodology practices and changes in approach
Ensures compliance with Xilinx engineering practice and methodologies.

Iterative Component Verification and Validation
Supports Test Engineering in the setting up of valid test verification criteria and plans at the system level
Creates and tracks schedules to ensure that component deliveries achieve technical and quality objectives per specifications in a timely manner
Ensures seamless component integration, device manufacturability, and sign-off acceptability based on formal verification test data
Mentors less experienced design engineers and leads experienced verification engineers in verification testing

Process Adaptation and Optimization
Provides design management (e.g., CAD department) on the efficiency of proposed methods
Adopts and applies Xilinx formal, cross-COE process innovation to facilitate standardization and advance efficient time-to-market practices
Adopts and applies Xilinx formal revision control
Solid knowledge of required scripting and automation
Mentors junior design engineers on emerging methods and how best to integrate these into practice

Verification and Validation
Creates verification plans at the block level
Understands protocols and standards associated with products
Collaborates with program management to verify that components meet technical specifications and quality requirements (e.g., power efficiency, area efficiency, ease of use)
Collaborates with other hardware and software groups to ensure effective component integration within the larger system
Supports Test Engineering or customer verification engineering teams in the setting up of valid test verification criteria and plans
Supports Applications Engineering in debugging customer issues
Troubleshoots component blocks as required to ensure milestone achievement and production-ready integration (e.g., specifications, performance, standards)
Manages regression suites for products, and contributes to the tool flow
Acts on verification test data to ensure seamless component integration, device manufacturability, and sign-off acceptability if applicable (e.g., customer sample feedback, iterative tape-out production turns involving 3rd parties)
When required, creates environment and infrastructure to test designs in a HW verification environment, and running test scenarios

Requirements Assessment
Solid understanding of FPGA building blocks and how they relate
Provides input into feasibility studies for proposed features
Understanding of customer tool flow and use models

Development and Validation
Prototypes and evaluates many competing implementations
Exercises strong analytical problem solving in block-level design (e.g., timing closure, area reduction, power optimization)
Accurately documents and effectively communicates design decisions and rationale

Development Process
Adapts design implementation methods to latest standards
Develops customization scripts for local optimization
Works effectively with evolving tool sets

Design Requirements Assessment
Assesses proposed component features to help determine cost-effectiveness and feasibility
Provides input to system architects in shaping and formalizing component roadmaps, resource needs, and milestones
Can properly analyze how all the elements of a design solution fit together
Can perform an End to End System performance analysis
Can properly evaluate internal and 3rd party IP solutions against requirements
Assesses proposed component features to help determine cost-effectiveness and feasibility
Provides input in shaping and formalizing component roadmaps, resource needs, and milestones
Present design decisions in a constructive and professional way before peers and direct management
May interact directly with customers as required

Design Enablement (Tools/System/Practice)
Exercises technical innovation in the use of standard design implementation tools and methods (e.g., circuit techniques)
Actively explores innovative design implementation tools or methods or their impact on implementation design practices (e.g., process excursions, boundary excess, signal passing of different voltages)
Stays current with and proposes the internal use of industry approaches, algorithms, and practices
Exercises a solid understanding of how circuit blocks are architected, developed, integrated, and verified through testing to achieve specification-compliant deliverables (e.g., CAD modeling, RTL coding, circuit architectures, building circuit specifications, applying simulation techniques, implementing verification testing methods)
Capable of mentoring junior engineers in the tips and tricks of tools used at Xilinx.
Applies technical innovation in the use of standard design implementation tools and methods (system portioning).
MS in Electrical Engineering
2 or more years of industry experience in mixed signal or high speed digital design
Skilled at programming and developing Verilog
Experience with standard cell based design and verification
Familiarity with static timing analysis tools
The ideal candidate will also be familiar with mixed signal blocks such as PLLs and DLLs


http://careers.xilinx.com/jobs/senior-design-engineer-3379