Xilinx FDST Verification group is looking for a Staff Design Verification Engineer to provide technical leadership and contribution on high speed Memory Controller IP Verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR, RLD, QDR, and HBM Memory Controller IP designs.

The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on Memory Controllers (DDR, LPDDR, RLDRAM, QDR, HBM), high performance IPs and/or SOC designs.
Require BS w/ 7+ yrs or MS w/ 5+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering or Computer Science.

Require hands on experience with verification of state of the art memory controllers such as DDR, LPDDR, RLDRAM and QDR, and HBM. Requires strong understanding of current memory controller protocols and calibration (DDR3/4, LPDDR3/4, RLDRAM3, QDR2, QDRIV, HBM-Gen1/2), JEDEC specification, board skew and jitter modeling.

Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.

Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.

Require experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.

Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.

Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.

Experience with FPGA programming and software is a plus.

Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.

Experience with gate level simulation, power verification, reset verification, contention checking is a plus.

Experience with silicon debug at the tester and board level, is a plus.